Design eng 4Lattice Semiconductor
Workplace: MetroManila, Manila, Makati
Salary: Agreement
Work form: Full time
Posting Date: 11/11/2025
Deadline: 14/02/2021
Description :
Engineer will develop comprehensive verification plans, clear metrics and continuously measure progress again the plan throughout the project. Testing can be done by writing Verilog or UVM testbench and running simulations or perform Hardware validation on an actual FPGA device. Engineeer is also expected to develop verification components as needed. The ideal candidate may also act as a technical lead and help develop best practices and world class methods for verification.
This position is for a Senior Design Verification Engineer in Lattice Philippines (LMN) working on verification of soft IPs targeted for Lattice FPGAs.
Verify RTL and gate-level designs using standard FPGA synthesis and simulation tools
Target designs to Lattice programmable devices using Lattice FPGA Software
Develop testbench and tests to verify the soft IPs
Ensure quality technical documentation
Work with Lattice Silicon and SW development to resolve IP/Si/SW issues
Reporting of metrics, implementing and monitoring improvement initiatives
Requirement:
10+ years experience in Digital Design and Verification, Verilog, System Verilog, C/C++
Expertise in DDR, PCIe, Ethernet, AMBA, and serial communication protocols is desired
Domain Knowledge in Machine Learning, Embedded System, Video and Audio systems a big plus
Good teamwork and able to collaborate with multi-site teams
Good written and verbal communication skills
Behaviors : Enthusiastic: Shows intense and eager enjoyment and interest
Team Player: Works well as a member of a group
Innovative: Consistently introduces new ideas and demonstrates original thinking
Motivation : Self-Starter: Inspired to perform without outside help
Ability to Make an Impact: Inspired to perform well by the ability to contribute to the success of a project or the organization
Flexibility: Inspired to perform well when granted the ability to set your own schedule and goals
Education : Bachelors
Experience : 10 years: Digital Design and Verification, Verilog, System Verilog, C/C++
Lattice Semiconductor
Engineer will develop comprehensive verification plans, clear metrics and continuously measure progress again the plan throughout the project. Testing can be done by writing Verilog or UVM testbench and running simulations or perform Hardware validation on an actual FPGA device. Engineeer is also expected to develop verification components as needed. The ideal candidate may also act as a technical lead and help develop best practices and world class methods for verification.
This position is for a Senior Design Verification Engineer in Lattice Philippines (LMN) working on verification of soft IPs targeted for Lattice FPGAs.
Verify RTL and gate-level designs using standard FPGA synthesis and simulation tools
Target designs to Lattice programmable devices using Lattice FPGA Software
Develop testbench and tests to verify the soft IPs
Ensure quality technical documentation
Work with Lattice Silicon and SW development to resolve IP/Si/SW issues
Reporting of metrics, implementing and monitoring improvement initiatives
Requirement:
10+ years experience in Digital Design and Verification, Verilog, System Verilog, C/C++
Expertise in DDR, PCIe, Ethernet, AMBA, and serial communication protocols is desired
Domain Knowledge in Machine Learning, Embedded System, Video and Audio systems a big plus
Good teamwork and able to collaborate with multi-site teams
Good written and verbal communication skills
Behaviors : Enthusiastic: Shows intense and eager enjoyment and interest
Team Player: Works well as a member of a group
Innovative: Consistently introduces new ideas and demonstrates original thinking
Motivation : Self-Starter: Inspired to perform without outside help
Ability to Make an Impact: Inspired to perform well by the ability to contribute to the success of a project or the organization
Flexibility: Inspired to perform well when granted the ability to set your own schedule and goals
Education : Bachelors
Experience : 10 years: Digital Design and Verification, Verilog, System Verilog, C/C++
Lattice Semiconductor
Other Info
Makati City, Metro Manila
Permanent
Full-time
Permanent
Full-time
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Lattice Semiconductor
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