senior design Verification engineerLattice Semiconductor
Workplace: Muntinlupa
Salary: Agreement
Work form: Full time
Posting Date: 06/01/2026
Deadline: 04/12/2022
Description :
Design Verification Engineer will be responsible for verifying all design views from behavioral hard IP up to Full chip SoC level. The engineer should be able to create testplan, design and architect testbench, do functional simulation, analyze and debug the design, communicate all findings to the design team and extract verification metrics to sign-off the design.
Job Detailed Description
Develop comprehensive verification plans, clear metrics and continuously measure progress against the plan throughout the project
Verify design blocks, sub systems and full chip using assertion-based verification, formal verification, directed tests and randomized tests
Understand the specifications, use cases and develop System Verilog and 'C' based testbenches in UVM environment
Design and develop testbench components such as Universal Verification Components, BFMs and verification tools
Define and design verification regression environment
Perform Functional coverage, RTL code coverage, assertion coverage, and gate level simulations
Collaborate with design engineers, IP developers and SW developers to deliver high quality SoC verification on aggressive time schedules
Develop best practices and world class methods for SoC verification
Requirement:
6-8 years Digital Design Verification Related Experience
Bachelor or Masters Degree in Computer Science, Computer Engineering, Electronics and Electrical Engineer
Skill in debugging and analyzing complex digital design
Experience in HDL and HVL Languages and Methodologies
Knowledge in ASIC/FPGA/SoC verification or development cycle
Knowledge in simulation tools like Cadence IES/XCELIUM, Synopsys VCS or Mentor's Questa
Hands-on experience in Python, Perl or Shell Scripting, TCL and Make.
Strong communication, analytical and documentation skills and ability to interface with other groups/site
Stay up to date on industry trends and direction of verification technology development
Education : Bachelors of Engineering
Experience : 6 years: Digital Design Verification Related Experience
Lattice Semiconductor
Design Verification Engineer will be responsible for verifying all design views from behavioral hard IP up to Full chip SoC level. The engineer should be able to create testplan, design and architect testbench, do functional simulation, analyze and debug the design, communicate all findings to the design team and extract verification metrics to sign-off the design.
Job Detailed Description
Develop comprehensive verification plans, clear metrics and continuously measure progress against the plan throughout the project
Verify design blocks, sub systems and full chip using assertion-based verification, formal verification, directed tests and randomized tests
Understand the specifications, use cases and develop System Verilog and 'C' based testbenches in UVM environment
Design and develop testbench components such as Universal Verification Components, BFMs and verification tools
Define and design verification regression environment
Perform Functional coverage, RTL code coverage, assertion coverage, and gate level simulations
Collaborate with design engineers, IP developers and SW developers to deliver high quality SoC verification on aggressive time schedules
Develop best practices and world class methods for SoC verification
Requirement:
6-8 years Digital Design Verification Related Experience
Bachelor or Masters Degree in Computer Science, Computer Engineering, Electronics and Electrical Engineer
Skill in debugging and analyzing complex digital design
Experience in HDL and HVL Languages and Methodologies
Knowledge in ASIC/FPGA/SoC verification or development cycle
Knowledge in simulation tools like Cadence IES/XCELIUM, Synopsys VCS or Mentor's Questa
Hands-on experience in Python, Perl or Shell Scripting, TCL and Make.
Strong communication, analytical and documentation skills and ability to interface with other groups/site
Stay up to date on industry trends and direction of verification technology development
Education : Bachelors of Engineering
Experience : 6 years: Digital Design Verification Related Experience
Lattice Semiconductor
Other Info
Alabang, Muntinlupa City
Permanent
Full-time
Permanent
Full-time
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Lattice Semiconductor
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