asi C/layout des eng 2Lattice Semiconductor
Workplace: MetroManila, Manila, Makati
Salary: Agreement
Work form: Full time
Posting Date: 10/11/2025
Deadline: 10/02/2021
Description :
The role includes IP block support and/or ownership, fullchip task support, chip-level layout integration, methodology improvement participation, and resource management and schedule definition to implement assigned layout tasks. Duties include but not limited to custom layout of ECO (Engineering Change Order) and LCO (Layout Change Order), verification of cells up to chip-level physical verification (e.g. DRC, LVS, ESD, DFM, Ant, EMIR, etc.), meet or beat task schedule, prompt resolution to technical issues related to layout, clear communication to appropriate stakeholders, and administrative tasks (e.g. task schedule definition).
Accountabilities:
Create and/or execute floorplanning, block estimates and layout of analog, mixed-signal and custom digital cells.
Work effectively with circuit designers to understand key layout constraints.
Proactively collaborate with CAD group as issues arise.
Hold layout quality reviews of completed cells, macros and chip-level.
Recognize layout considerations pertaining to device matching, noise, shielding, WPE/STI and latch-up in analog, mixed signal and digital circuit.
Required Skills/Experience:
At least 4 yrs of solid Custom Layout Engineering industry experience.
Custom layout of IP blocks to Fullchip layout integration using Cadence Virtuoso and full physical verification (DRC, LVS, ESD, Antenna, DFM, EMIR, etc) using Mentor Graphics Calibre.
SKILL scripting skill is a plus.
Education : Bachelors of Engineering
Experience : 4 years: Custom Layout Engineering industry experience.
Lattice Semiconductor
The role includes IP block support and/or ownership, fullchip task support, chip-level layout integration, methodology improvement participation, and resource management and schedule definition to implement assigned layout tasks. Duties include but not limited to custom layout of ECO (Engineering Change Order) and LCO (Layout Change Order), verification of cells up to chip-level physical verification (e.g. DRC, LVS, ESD, DFM, Ant, EMIR, etc.), meet or beat task schedule, prompt resolution to technical issues related to layout, clear communication to appropriate stakeholders, and administrative tasks (e.g. task schedule definition).
Accountabilities:
Create and/or execute floorplanning, block estimates and layout of analog, mixed-signal and custom digital cells.
Work effectively with circuit designers to understand key layout constraints.
Proactively collaborate with CAD group as issues arise.
Hold layout quality reviews of completed cells, macros and chip-level.
Recognize layout considerations pertaining to device matching, noise, shielding, WPE/STI and latch-up in analog, mixed signal and digital circuit.
Required Skills/Experience:
At least 4 yrs of solid Custom Layout Engineering industry experience.
Custom layout of IP blocks to Fullchip layout integration using Cadence Virtuoso and full physical verification (DRC, LVS, ESD, Antenna, DFM, EMIR, etc) using Mentor Graphics Calibre.
SKILL scripting skill is a plus.
Education : Bachelors of Engineering
Experience : 4 years: Custom Layout Engineering industry experience.
Lattice Semiconductor
Other Info
Makati City, Metro Manila
Permanent
Full-time
Permanent
Full-time
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Lattice Semiconductor
About the company
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