asi C/layout des eng 4Lattice Semiconductor
Workplace: Muntinlupa
Salary: Agreement
Work form: Full time
Posting Date: 24/01/2026
Deadline: 03/03/2022
Description :
Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development. Create high-quality analog, mixed-signal and custom digital layout. At least 8+ years of proven in-depth experience on custom and semi-custom layout of various IPs including memory and array cells, analog and mixed-signal blocks, Serdes, and up to chip level layout integration. The role includes project layout ownership covering IP layout mgt and FC integration, initiating methodology improvement, contributing to organizational development, and performance management. Duties include but not limited to custom layout of ECO (Engineering Change Order) and LCO (Layout Change Order), cells/IP/chip-level physical verification (e.g. DRC, LVS, ESD, DFM, Ant, EMIR, etc.), meet or beat task schedule, prompt resolution to technical issues related to layout, clear communication to appropriate stakeholders, and administrative tasks (e.g. task schedule definition). Run and analyze LPE, pre/post-layout simulations, IP views such as power and timing files.
Lead a team to successfully deliver custom layout of IP platform development, FC integration and physical verification until TO and project resources/schedule management.
Create floor plan, block estimates and layout of analog, mixed-signal and custom digital cells.
Work effectively with circuit designers to understand key layout constraints.
Proactively collaborate with CAD group as issues arise.
Hold layout quality reviews of completed cells, IP blocks and FC physical integration.
Recognize layout considerations pertaining to device matching, noise, shielding, ESD and latch-up in analog, mixed signal and digital circuit.
Run and analyze LPE, pre/post-layout simulations and IP views such as power and timing files.
REQUIREMENTS:
At least 8 yrs of solid Custom Layout Engineering industry experience.
Custom layout of IP blocks up to full chip layout integration using Cadence Virtuoso and full physical verification (DRC, LVS, ESD, Antenna, DFM, EMIR, etc) using Mentor Graphics Calibre.
Experience in generating LPE and simulations, IP views such as timing and power files, is a plus.
SKILL scripting skill is a plus.
Lower FinFET tech node experience is a plus.
Ability to manage performance of project team members and direct reports.
Education : Bachelors of Engineering
Experience : 0 years: Experience in generating LPE and simulations, IP views such as timing and power files, is a plus
0 years: Custom layout of IP blocks up to full chip layout integration using Cadence Virtuoso and full physical verification (DRC, LVS, ESD, Antenna, DFM, EMIR, etc) using Mentor Graphics Calibre
8 years: solid Custom Layout Engineering industry experience
Lattice Semiconductor
Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development. Create high-quality analog, mixed-signal and custom digital layout. At least 8+ years of proven in-depth experience on custom and semi-custom layout of various IPs including memory and array cells, analog and mixed-signal blocks, Serdes, and up to chip level layout integration. The role includes project layout ownership covering IP layout mgt and FC integration, initiating methodology improvement, contributing to organizational development, and performance management. Duties include but not limited to custom layout of ECO (Engineering Change Order) and LCO (Layout Change Order), cells/IP/chip-level physical verification (e.g. DRC, LVS, ESD, DFM, Ant, EMIR, etc.), meet or beat task schedule, prompt resolution to technical issues related to layout, clear communication to appropriate stakeholders, and administrative tasks (e.g. task schedule definition). Run and analyze LPE, pre/post-layout simulations, IP views such as power and timing files.
Lead a team to successfully deliver custom layout of IP platform development, FC integration and physical verification until TO and project resources/schedule management.
Create floor plan, block estimates and layout of analog, mixed-signal and custom digital cells.
Work effectively with circuit designers to understand key layout constraints.
Proactively collaborate with CAD group as issues arise.
Hold layout quality reviews of completed cells, IP blocks and FC physical integration.
Recognize layout considerations pertaining to device matching, noise, shielding, ESD and latch-up in analog, mixed signal and digital circuit.
Run and analyze LPE, pre/post-layout simulations and IP views such as power and timing files.
REQUIREMENTS:
At least 8 yrs of solid Custom Layout Engineering industry experience.
Custom layout of IP blocks up to full chip layout integration using Cadence Virtuoso and full physical verification (DRC, LVS, ESD, Antenna, DFM, EMIR, etc) using Mentor Graphics Calibre.
Experience in generating LPE and simulations, IP views such as timing and power files, is a plus.
SKILL scripting skill is a plus.
Lower FinFET tech node experience is a plus.
Ability to manage performance of project team members and direct reports.
Education : Bachelors of Engineering
Experience : 0 years: Experience in generating LPE and simulations, IP views such as timing and power files, is a plus
0 years: Custom layout of IP blocks up to full chip layout integration using Cadence Virtuoso and full physical verification (DRC, LVS, ESD, Antenna, DFM, EMIR, etc) using Mentor Graphics Calibre
8 years: solid Custom Layout Engineering industry experience
Lattice Semiconductor
Other Info
Alabang, Muntinlupa City
Permanent
Full-time
Permanent
Full-time
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Lattice Semiconductor
About the company
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